1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an in-plane switching liquid crystal display (IPS LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
A liquid crystal display device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce an image. Liquid crystal molecules have a definite orientational alignment as a result of their long, thin shapes. The alignment direction can be controlled by an applied electric field. Specifically, as an applied electric field changes, so does the alignment of the liquid crystal molecules. Due to the optical anisotropy, the refraction of incident light depends on the alignment direction of the liquid crystal molecules. Thus, by properly controlling an applied electric field, a desired light image can be produced.
An electric field is induced by a voltage difference between a pixel electrode and a common electrode. An in-plane switching IPS LCD device having the pixel electrode and the common electrode on the same substrate has been widely developed and used because the IPS LCD device has a wide viewing angle. A detailed explanation of a related art IPS LCD device and its operation modes will be provided with reference to the following figures.
FIGS. 1A and 1B are cross-sectional views of an IPS LCD device according to the related art, and illustrate operations of liquid crystal molecules for the IPS mode in OFF and ON states.
As shown in the figures, first and second substrates 10 and 60 are spaced apart from and face each other. A pixel electrode 40 and a common electrode 45 are formed on the first substrate 10. Liquid crystal molecules 52 of a liquid crystal layer 50 are arranged along a lateral electric field, which is parallel to the first and second substrates 10 and 60, and induced between the pixel electrode 40 and the common electrode 45.
FIG. 1A conceptually illustrates an OFF state operation mode for the related art IPS LCD device. In the OFF state, because there is no electric field between the two electrodes 40 and 45, the liquid crystal molecules 52 maintain an initial arrangement according to an alignment layer, which is made by a method such as a rubbing. Thus, the long axes of the liquid crystal molecules 52 are parallel to the common and pixel electrodes 40 and 45 on the first substrate 10.
FIG. 1B conceptually illustrates an ON state operation mode for the related art IPS LCD device. In the ON state, a lateral electric field 56 parallel to the first and second substrates 10 and 60 is generated between the pixel and common electrodes 40 and 45. Thus, the liquid crystal molecules 52b between the pixel and common electrodes 40 and 45 are aligned such that long axes thereof are parallel to the substrates 10 and 60 and perpendicular to the pixel and common electrodes 40 and 45, while the liquid crystal molecules 52a over the pixel and common electrodes 40 and 45 maintain an initial arrangement e.g., parallel to the pixel and common electrodes 40 and 45 because an electric field vertical to the substrates 10 and 60 is induced over the pixel and common electrodes 40 and 45.
As stated above, the IPS LCD device uses the lateral electric field that results from the pixel and common electrodes 40 and 45 being formed on the same substrate, e.g., the first substrate 10. The IPS LCD device has a wide viewing angle and low color dispersion.
FIG. 2 is a plan view of a related art in-plane switching liquid crystal display (IPS LCD) device. As illustrated in FIG. 2, gate lines 120 are formed horizontally in the context of the figure, and data lines 130 extend vertically in the context of the figure. The gate and data lines 120 and 130 cross each other to define a pixel region. A thin film transistor T is connected to the gate line 120 and the data line 130 as a switching element. A pixel electrode 140 is connected to the thin film transistor T, and a common electrode 145 for generating a lateral electric field with the pixel electrode 140 is also formed. The common electrode 145 is connected to a common line 147, which is parallel to the gate line 120.
The gate line 120 and the data line 130 are connected to a gate pad 125 and a data pad 135, respectively. The gate pad 125 and the data pad 135 are connected to outer gate and data driver integrated circuits (not shown), and receive scanning and video signals from the gate and data driver integrated circuits, respectively. Thus, the scanning signals are applied to the gate line 120 through the gate pad 125 and the video signals are applied to the data line 130 through the data pad 135.
The thin film transistor T includes a gate electrode 121 extending from the gate line 120, a semiconductor layer 115 over the gate electrode 121, a source electrode 131 extending from the data line 130 and overlapping the semiconductor layer 115, and a drain electrode 133 spaced apart from the source electrode 131. The thin film transistor T turns ON/OFF depending on the scanning signals transmitted to the gate electrode 121, and when the thin film transistor T turns ON, the video signals are transmitted from the source electrode 131 to the drain electrode 133.
The pixel electrode 140 is connected to the drain electrode 133, and the common electrode 145 is parallel to the pixel electrode 140. The common electrode 145 alternates with the pixel electrode 140. Additionally, the common electrode 145 is connected to the common line 147 through a contact hole 149, and thus receives common signals.
The common line 147 is adjacent to a previous gate line 120, and is formed through the same process as the gate line 120. That is, a metal layer is deposited on a substrate and then is patterned to thereby form the gate line 120 and the common line 147. The adjacent common and gate lines 147 and 120 have a distance of about 10 μm therebetween.
To form the gate and common lines 120 and 147, an etching process using an etchant is performed. During the etching process, an electrical short may occur between the adjacent gate line 120 and common line 147 due to fine residues. For example, if the adjacent common and gate lines are spaced apart with a distance of 8 μm to 12 μm, 20˜60% may be electrically shorted.